PCB via design skills sharing
Via is one of the important components of multilayer PCB, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. Simply put, every hole on the PCB can be called a via. From the point of view of function, vias can be divided into two categories: one is used for electrical connections between layers; the other is used for fixing or positioning devices. In terms of process, vias are generally divided into three categories, namely blind vias, buried vias and through vias.
Blind vias are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via. The third type is called a through hole, which penetrates the entire circuit board and can be used for internal interconnection or as a component mounting positioning hole. Because the through hole is easier to realize in the process and the cost is lower, it is used in most printed circuit boards instead of the other two kinds of through holes. The via holes mentioned below, unless otherwise specified, are considered as via holes.
1. From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper. For example, the thickness (through hole depth) of a normal 6-layer PCB board is about 50Mil, so the minimum drilling diameter that PCB manufacturers can provide can only reach 8Mil.
Second, the parasitic capacitance of the via hole itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, and the thickness of the PCB board is T, The dielectric constant of the board substrate is ε, and the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1) The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce The speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, the rise time change caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. It can be seen from these values ??that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.
3. Parasitic inductance of vias Similarly, there are parasitic inductances along with parasitic capacitances in vias. In the design of high-speed digital circuits, the damage caused by parasitic inductances of vias is often greater than the impact of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can simply calculate the approximate parasitic inductance of a via with the following formula: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the center The diameter of the hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so that the parasitic inductance of the via will double.
4. Via design in high-speed PCB. Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negatives to circuit design. effect. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design as much as possible:
1. From the two aspects of cost and signal quality, select a reasonable size of vias. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.
2. The two formulas discussed above can be concluded that the use of a thinner PCB is beneficial to reduce the two parasitic parameters of the via.
3. Try not to change the layers of the signal traces on the PCB board, that is to say, try not to use unnecessary vias.
4. The power and ground pins should be drilled nearby, and the lead between the via and the pin should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.
5. Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB board. Of course, the design needs to be flexible. The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially when the density of vias is very high, it may lead to the formation of a break groove that separates the loop in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.
Blind vias are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via. The third type is called a through hole, which penetrates the entire circuit board and can be used for internal interconnection or as a component mounting positioning hole. Because the through hole is easier to realize in the process and the cost is lower, it is used in most printed circuit boards instead of the other two kinds of through holes. The via holes mentioned below, unless otherwise specified, are considered as via holes.
1. From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper. For example, the thickness (through hole depth) of a normal 6-layer PCB board is about 50Mil, so the minimum drilling diameter that PCB manufacturers can provide can only reach 8Mil.
Second, the parasitic capacitance of the via hole itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, and the thickness of the PCB board is T, The dielectric constant of the board substrate is ε, and the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1) The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce The speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, the rise time change caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. It can be seen from these values ??that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.
3. Parasitic inductance of vias Similarly, there are parasitic inductances along with parasitic capacitances in vias. In the design of high-speed digital circuits, the damage caused by parasitic inductances of vias is often greater than the impact of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can simply calculate the approximate parasitic inductance of a via with the following formula: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the center The diameter of the hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so that the parasitic inductance of the via will double.
4. Via design in high-speed PCB. Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negatives to circuit design. effect. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design as much as possible:
1. From the two aspects of cost and signal quality, select a reasonable size of vias. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.
2. The two formulas discussed above can be concluded that the use of a thinner PCB is beneficial to reduce the two parasitic parameters of the via.
3. Try not to change the layers of the signal traces on the PCB board, that is to say, try not to use unnecessary vias.
4. The power and ground pins should be drilled nearby, and the lead between the via and the pin should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.
5. Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB board. Of course, the design needs to be flexible. The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially when the density of vias is very high, it may lead to the formation of a break groove that separates the loop in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.